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JET60200's avatar
JET60200
Icon for Contributor rankContributor
6 years ago

How to generate a 644.53125 MHz clock on the A10SoC Dev Kit Board, for 10GE (SFP+) verification ?

Hello, ​ I want to test 10GE MAC IP on A10SOC Dev Kit SFP+ port. ​ According to ug-20016, for 10ge case, one clock 644.53125MHZ is needed to feed into A10 “dedicated transceiver”. ​ Unfo...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As I look into the UG-20016 | 2019.09.23, it seems like the hardware validation was done using Intel Arria 10 GX Transceiver Signal Integrity Development Kit but not the A10 SOC devkit. As I look into the A10 SOC devkit, seems like there is no specific refclk source of 644.53125MHz for the 10GE example design testing. Sorry for the inconvenience. You might want to use A10GX SI devkit for the validation as per the user guide.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin