Forum Discussion
Ahmed_H_Intel1
Frequent Contributor
7 years agoHi,
So if you are booting from the EPCS you can use the following:
1- Use "small Hello wold template" which turns off all the unnecessary libraries
2- Use optimization -O2 in the project settings.
These two options will give you the smallest code size of your application. If you still facing the same error you can use the XIP "Execute In Place" to save more size of the RAM which won't copy the .text region of the code to RAM (If the EPCS can fit the design)
In case if the EPCS cannot fit the design (FPGA+Zipped app) you can try:
- To configure the FPGA from another memory.
- Upgrade the EPCS flash. Configure the FPGA and Boot NIOS from EPCS with XIP on RAM.
- Upgrade the RAM and Configure the FPGA from EPCS and Run the NIOS on RAM.
Otherwise I apologize if the design still out of memory, I have no clue to shrink it more than this to fit into the RAM and EPCS. Please let me know how can I help you.
Regards,