Forum Discussion
MSteg2
New Contributor
7 years agoWe have an 8MB EPCS Flash and 16MB RAM and he RESET vector points to EPCS (BOOT).
- Lower 1MB of this is FPGA and BOOT
- Upper 7MB of this is our (zipped) APP ... which is built with SAME FPGA as BOOT (but does not have another copy)
At Power Up:
- The FPGA is loaded by H/W from EPCS Flash
- The BOOT is copied into RAM and Vectored to in RAM by H/W
- BOOT sees APP image in EPCS is VALID and unzips it to RAM and jumps to it (BOOT is now DONE)
- APP image runs out of 16MB RAM (using FPGA loaded from BOOT)