New Contributor
New ContributorHey, thanks for your response! Some follow up questions inline with your questions:
Check the FPGA part number, Is it same?
>> yes, 10M08 Evaluation Kit and 10M08E144 has been used in the designed board as well.
Are you able to “auto-detect” to detect the physical device in the JTAG chain?
>> NO, check out the image attached at the end.
Check the status of nCE,nCONFIG and nSTATUS pins.
>> CAN WE GET A REFERENCE MANUAL FOR THE 10M08 EVAL KIT? WHAT IS THE EXPECTED OUTPUT FOR THESE PINS WHEN JTAG CHAIN IS PROPERLY DETECTED?
Check pull-up/pull-down resistors and also check the soldering contact.
>> FOR WHICH I/O PORT?
Check the power supplies are ramped up to the appropriate voltage level according to the POR requirements. Refer below link for POR.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_pwr.pdf
>> Could you help by providing us with a schematic diagram? Where are the test pins/ pads available in the Evaluation Board at least?
Attached some image on error message and pin status.
>>
I'd be very grateful for any links on testing and debugging these problems, thank you!
Regular ContributorHi,
I am realy confused,
Are you using self designed board? or Max 10 Evaluation board?
please check the Configuration troubleshooting refer below link.
https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/devices/cfg-index/fpga-configuration-troubleshooter.html
Are you able to “auto-detect” to detect the physical device in the JTAG chain?
>> NO, check out the image attached at the end.
>>>I can see 10M08SA and 10M08SC , is it for Max 10 Evaluation board
Check the status of nCE,nCONFIG and nSTATUS pins.
>> CAN WE GET A REFERENCE MANUAL FOR THE 10M08 EVAL KIT? WHAT IS THE EXPECTED OUTPUT FOR THESE PINS WHEN JTAG CHAIN IS PROPERLY DETECTED?
>>> you can find the information from from configuration user guide or from pin connection guidelines
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf
Check pull-up/pull-down resistors and also check the soldering contact.
>> FOR WHICH I/O PORT?
>>>FPGA Configuration pins(PIN connection guidelines) and your board power supply components.
Check the power supplies are ramped up to the appropriate voltage level according to the POR requirements. Refer below link for POR.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_pwr.pdf
>> Could you help by providing us with a schematic diagram? Where are the test pins/ pads available in the Evaluation Board at least?
FPGA pins like VCC, VCCA , VCCIO also configuration pins like TCK,TDI, TMS & nCE,nCONFIG and nSTATUS pins
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-max-10-evaluation.html
Regards
Anand
Regular ContributorThe Eval Board is being recognized in the JTAG chain but the self designed one is not. Any way to fix the JTAG
>>It means JTAG chain not working.
May be, device not powered, components not properly connected or defective. Refer pin connection guidelines
please check the FPGA pins like VCC, VCCA , VCCIO also configuration pins like TCK,TDI, TMS & nCE, nCONFIG and nSTATUS pins.
please check the Configuration troubleshooting refer below link.
https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/devices/cfg-index/fpga-configuration-troubleshooter.html
Regards
Anand
New ContributorHi, sorry for the confusion but we're using BOTH. We need to debug the self designed board and the Eval Board is just for reference.
The Eval Board is being recognized in the JTAG chain but the self designed one is not. Any way to fix the JTAG recognition issue there?
Thank you for your help.
