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NCart2's avatar
NCart2
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6 years ago

How can I generate license for Stratix 10 TX development kit for Quartus Pro Edition 19.1?

Hi,

I'm a Digital IC Designer of eSilicon Ltd and we have a Stratix 10 TX development board. Buying this board, we have also a 1-year license for Quartus Pro Edition.

We are trying to map the design examples of e-tile channels on this board but we have some problems when we execute the test by using the system console. Due that these design examples are provided for the Quartus 18.1.1 version, we would try to use the last version of the software. Unfortunately, after we generate the design example and try to map it on the board, at the final phase Quartus does not generate the SOF file due to license problems. Why do we have these problems?

Kind regards,

Nicola Carta.

3 Replies

  • AR_A_Intel's avatar
    AR_A_Intel
    Icon for Super Contributor rankSuper Contributor
    6 years ago
    Hello Welcome to INTEL forum. Intel license is backwards compatibility and will not support upper Quartus version. In your case your license support until version 18.1.1. Need to apply new Quartus Subscription Edition license for version 19.1 Kindly contact your nearest Altera sales person or distributor to purchase a valid license file. To order by phone: >>In the United States and Canada, call Telesales at 1-888-800-0631. >>Outside the United States or Canada, contact your local sales representative or distributor. Alternatively, you could also request temporary 60-days evaluation license. Please find the contact for our sales and distributor near you from link below: https://www.altera.com/about/contact/contact.html buy online. https://www.altera.com/buy/design-software.html
    • NCart2's avatar
      NCart2
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hi,

      we are following the design example user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-etile-hip-ethernet.pdf) for the Stratix 10 TX (device 1ST280EY2F55E2VGS1). We have generated two examples for the e-tile:

      • single 10G/25G channel with AN/LT and PCS+MAC configuration (AN and LT on reset);
      • 100GE channel with AN/LT and PCS+MAC configuration (AN and LT on reset).

      Both examples have been mapped on the board and we have exploited the "main_script.tcl/main.tcl" by using the system console but it seems that they do not work properly. In particular, in the 10G/25G usecase, c3_elane_xcvr_loopback_test passed correctly while c3_elane_traffic_basic_test failed. Moreover, we are trying to access on the KR4 registers of the channel 0 to enable autonegotiation or reset it by sw but the system console return "deadc0de". If we try to access on registers of the remaining address space (for instance, RX PCS registers), the system answers as expected. How can we generate the e-tile in order that it works properly to have for example 10G/25G with AN/LT?

      Thank you very much.

      Kind regards,

      Nicola Carta.

  • AR_A_Intel's avatar
    AR_A_Intel
    Icon for Super Contributor rankSuper Contributor
    6 years ago
    Apologize the delay as I was out of office recently. Can you provide your license.dat file, error message screen shot and assembler file for checking? And you can also reply/attach your file in private message.