Forum Discussion

Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Highspeed LVDS ADC interface to arria 10 fpga

Hi, I am using high speed ADC (ADS62P25IRGCT) with arria10, Output of ADC is LVDS, i want single ended input in FPGA, GPIO ip: is Not suitable as specified in datasheet. GPIO Intel FPGA IP U...
  • Ash_R_Altera's avatar
    Ash_R_Altera
    5 years ago

    Yes, you can use it to convert the differential signal to single ended and implement the DDR data capture logic to it. The IP basically configures the IOE element of the device.

    Regards


Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

The GPIO Intel FPGA IP can be configured to be used with a differential buffer and DDIO as Register mode. You can assign LVDS IO standard to the input pin.


Regards