Forum Discussion

jackgreen's avatar
jackgreen
Icon for New Contributor rankNew Contributor
5 years ago

FPGA Opencl caching for CPU access to shared memory through ACP port

I am doing a project on CycloneV soc which involves transferring large amount of data from memory to FPGA. As DMA needs to work with physically contiguous memory, I copied data to the share memory fi...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Yes, have you tried apply the best practice guide previously? It is recommended that you do so. I hope that helps.