Forum Discussion

jackgreen's avatar
jackgreen
Icon for New Contributor rankNew Contributor
5 years ago

FPGA Opencl caching for CPU access to shared memory through ACP port

I am doing a project on CycloneV soc which involves transferring large amount of data from memory to FPGA. As DMA needs to work with physically contiguous memory, I copied data to the share memory fi...
jackgreen's avatar
jackgreen
Icon for New Contributor rankNew Contributor
5 years ago

Thanks for your reply!

However, I am satisfied with the performance of the kernel right now. And I really want to optimize the process where data is transferred to and from the shared memory. It costs much more time than the kernel running.