Forum Discussion
jackgreen
New Contributor
New ContributorFPGA Opencl caching for CPU access to shared memory through ACP port
I am doing a project on CycloneV soc which involves transferring large amount of data from memory to FPGA. As DMA needs to work with physically contiguous memory, I copied data to the share memory fi...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
Instead of trying to enable the CPU cache which does not guarantee the performance of moving your data, you could try and check the best practices in the optimizing memory access section to possibly improve the performance:
jackgreenThanks for your reply!
However, I am satisfied with the performance of the kernel right now. And I really want to optimize the process where data is transferred to and from the shared memory. It costs much more time than the kernel running.
