FFT Intel FPGA IP

Hi,

Thanks for your reply, the feedback of your requests are as follows:

1.The FPGA device is Agilex7: AGIB027R29A1E2VR0, Quartus version is Quartus-pro-24.3.0.212.

2.The simulator is vcsmx, following the standard simulation steps.

3.First I simulate the forward FFT, the input data is shown as Fig.1, and the simulation result is shown as Fig.2. After digit-reverse, the result is shown as Fig.3. The calculation result of python is shown as Fig.4, and we can see the results of calculation and simulation are consistent. Then I simply assert the inverse signal of FFT Intel FPGA IP, the input data is same as before, the simulation result is shown as Fig.5 (after digit-reverse), and the calculation results of python is shown as Fig.6. we can see the results are inconsistent. I have tried the Variable Size FFT Intel FPGA IP for the same calculation, the result is shown in Fig.7 (after bit-reverse), and we can see the results are consistent. As a result, I confirm the calculation result of python is correct, and the simulation result of Intel FPGA FFT IP is wrong.

4.I have tried set direction as reverse only, the results is same (wrong).

Best regards