Contributorexecute An814
Dear Support
I have the errors while generate HDL, I am using Quartus PRO 21. 3
I followed the AN814 instruction step by step all the way to Page 11, item 6.b.
Repeat step a. to generate HDL files for jesd204b_ed_qsys.qsys and
dl_count.qsys.
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_avmm_read declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_clk declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_avmm_waitrequest declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_avmm_write declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_reset declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_avmm_read declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_clk declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_avmm_waitrequest declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_avmm_write declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_reset declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: The system cannot be generated when there are errors.
Hi dsun01,
Just want to confirm that are you using the manual stated below for guidance?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an814.pdf
If yes, you should use Quartus Prime Pro Edition version 17.0 instead of Quartus PRO 21. 3.
The reference design requires that particular version.
Hope it helps.
Best regards,
Sheng
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
