Forum Discussion
Occasional Contributorerror message: can't fit into the design
Hi,
I have not modified the design which you have shared in previous post attachments.
- You can add Qspi and PLL in Qsys system(onchip.qsys/onchip.qip) and remove the pll.qip file from project and onchip.qip set as top level entity and compile. Attached the file do pin assignment and other configuration as per you requriment
For RSU design example (QSPI &PLL) look into design stores or follow an741 or check below video links
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an741.pdf
https://fpgacloud.intel.com/devstore/platform/?search=RSU&acds_version=any&family=max-10search for reference design.
https://www.youtube.com/watch?v=Qgwd8ftiTZc
https://www.youtube.com/watch?v=bAyqWWm1yLU
https://www.youtube.com/watch?v=r3wcgr3LmjA
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Regards
Anand
Regular ContributorHi AKAYA,
The device 10M25SAE144C8G is having only 1 PLL.Please check the image.
You can follow the suggestion given by @JOHI , use single PLL with multiple outputs depending frequency requirement.
Regards
Anand
Occasional Contributorthanks for the reply...
but can you tell me what exactly is the reason for the error...
I have used an ALTPLL IP with C0 as the compensated output....
- AnandRaj_S_Intel
Hi Akaya,
Fitter cannot place the specified node at the specified location which has been disabled to drive to the clock networks because the current package does not support it, or because it cannot be used when device migration is selected.
I guess, Initial design was for some other device from same family 10M25 which had 4-PLL and you have migrated to 10M25SAE144C8G which is having only 1 PLL because of which you are having error.
If you are using 10M25SAE144C8G device you can have 1-pll with 4-output max.
Check .qsf file for lines like set_location_assignment PLL_{number} -to "{path}"
set_location_assignment PLL_0 -to "{path}"
set_location_assignment PLL_1 -to "{path}"
set_location_assignment PLL_2-to "{path}"
set_location_assignment PLL_3 -to "{path}"
have set_location_assignment PLL_0 -to "{path}" and remove other line set_location_assignment PLL_1/2/3 -to "{path}" and Delete db and incremental_db folders and recompile the design and check.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand
- AKAYA
thank you for the reply....
I didn't change the device, am using the same device..
in the .qsf file does not contain any line like set_location_assignment PLL_{number}
can someone suggest me how to solve this
