Forum Discussion
Occasional Contributorerror message: can't fit into the design
Hi,
I have not modified the design which you have shared in previous post attachments.
- You can add Qspi and PLL in Qsys system(onchip.qsys/onchip.qip) and remove the pll.qip file from project and onchip.qip set as top level entity and compile. Attached the file do pin assignment and other configuration as per you requriment
For RSU design example (QSPI &PLL) look into design stores or follow an741 or check below video links
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an741.pdf
https://fpgacloud.intel.com/devstore/platform/?search=RSU&acds_version=any&family=max-10search for reference design.
https://www.youtube.com/watch?v=Qgwd8ftiTZc
https://www.youtube.com/watch?v=bAyqWWm1yLU
https://www.youtube.com/watch?v=r3wcgr3LmjA
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Regards
Anand
Regular ContributorHi,
Can i know which FPGA device(P/N) are you using?
This error say it all, your device support only 1 PLL but you are using 2 PLL.
To solve you can follow the suggestion given by @JOHI or change the device as per design requirement.
Please check below thread with similar issues which may help you.
https://forums.intel.com/s/question/0D50P00003yyTYJSA2/max-10-using-two-altpll?language=en_US
Regards
ARS
AKAYAthanks for the reply
am using 10M25SAE144C8G device. it shows a resource count of 4
I can't change the device. is there any other option....
