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PaulR1's avatar
PaulR1
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5 years ago

EMIF Avalon MM interface

Hi all, I have ported a customer design from a competitor chip to an Intel FPGA and in doing so I have had to make a 'converter' from their interface to the DDR controller they originally had into...
yoichiK_altera's avatar
yoichiK_altera
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5 years ago

Hi

As for the memory controller efficiency sequence address is the most efficiency pattern and random is not. When you issue the single write or read order the controller does not know if they are sequence address or not. Therefore the longer burst length is always the better efficiency you can get.