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Altera_Forum's avatar
Altera_Forum
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15 years ago

DMA on a DE0

Hi all, Can someone verify for me that they have DMA to SDRAM working on a DE0 board ? I've been trying to get it to work for a couple of days, but no joy. Here's how it's set up in SOPC builde...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Perhaps the DMA or bridge suffered from the same bug as the SGDMA used to as well and it was fixed in 11.0 (it's been a while so I forget). This bug would prevent the master from issuing a request until waitrequest is low so as you can imagine this could cause the master to get stuck. Masters shouldn't wait for waitrequest to de-assert so this was addressed in a few cores.

To make sure the memory timing has some slack (if you decide not to use Timequest constraints) I would try a few other clock phases to make sure you are not on the edge of not meeting timing.

Goodluck with the rest of your project.