DMA on a DE0

Well, since this is such a simple design, I decided to try out Quartus2 v11, and see if that helped matters, especially since you say the DMA ought not hang...

Long story short: it works in v11. I can't see anything that I'm doing differently (apart from minor things - there's a clock-bridge component rather than directly exporting the pll's scram clock). In any event, the last two times I've tried it, the SDRAM passes its DMA test as well as its CPU test...

http://www.0x0000ff.com/imgs/fpga/dma-success.png

Note that I'm testing the same memory-area as before. This is working at 100MHz as well, not just at the 50MHz I was trying on Quartus 10.1

Oh well, should have tried the later version earlier :( Still, glad it's working now :)

Simon