Hmm - ok, looking around the forum, I found: http://www.alteraforum.com/forum/showthread.php?t=1269&page=2 which has some fairly clear docs on how to constrain the SDRAM using Timequest, so if I did:
--- Quote Start ---
create_clock -period 20.000 -name ext_clk [get_ports {CLOCK_50}]
derive_pll_clocks
derive_clock_uncertainty
set sdram_clk gpu|the_altpll_0|sd1|pll7|clk[0]
create_generated_clock -name sdram_clk_pin
-source $sdram_clk -offset 0.5 [get_ports {sdram_clk}]
--- Quote End ---
... using a 0.5ns offset for PCB routing. Reading the datasheet (the DRAM on a DE0 is an A3V64S40ETP chip, with the speed-class -6, so it can run at 166MHz), and using CAS latency=3, it seems
- Max Clk-to-valid-output-delay = 5.4ns
- Min Output data-hold time = 2.5ns
- Min setup = 1.5ns
- Min hold = 1 ns
... so if I further add:
--- Quote Start ---
set_input_delay -clock sdram_clk_pin -max [expr 5.4 + 0.6]
[get_ports {DRAM_CAS_N DRAM_RAS_N DRAM_CS_N DRAM_WE_N DRAM_ADDR[*]}]
set_input_delay -clock sdram_clk_pin -min [expr 2.5 + 0.4]
[get_ports {DRAM_CAS_N DRAM_RAS_N DRAM_CS_N DRAM_WE_N DRAM_ADDR[*]}]
set_output_delay -clock sdram_clk_pin -max [expr 1.5 + 0.6]
[get_ports {DRAM_CAS_N DRAM_RAS_N DRAM_CS_N DRAM_WE_N DRAM_ADDR[*]}]
set_output_delay -clock sdram_clk_pin -min [expr -1.0 + 0.4)]
[get_ports {DRAM_CAS_N DRAM_RAS_N DRAM_CS_N DRAM_WE_N DRAM_ADDR[*]}]
--- Quote End ---
... it ought to self-constrain without me having to use a second clock with an offset ?
Questions:
- I don't really see why DRAM_BA and DRAM_{L,U}DQM aren't part of the ports listed. I'm following the recommendations in the document, but would love to know :)
- I'm guessing that the DRAM_DQ data lines aren't specified because they'll be latched at some time during the waveform that the other signals comprise, so they're less important to get synchronised.
- DRAM_CKE isn't mentioned anywhere either. Ought I be putting this signal into the list of ports above ?
Cheers
Simon
Honored Contributor
