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Ah you are correct, this whole time I thought the small memtest used the DMA. I think if you took the memtest code, and removed the flash testing stuff and switched the software over to using small printfs you could probably get it to fit in an 8k on-chip memory.
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I may give that a go, but I'm pretty sure I'm not over-writing anything at the moment - I'm printing out the addresses I'm using and...
- the MemDMATest is the last thing to allocate any RAM (for the DMA buffers) and they're well below the area I'm testing.
- the stack ought to be nowhere near where I'm testing either. The Memory extends from 0x800000 to 0xFFFFFF, and I'm only testing from 0xA00000 to 0xB00000 at the moment.
One of the runs looks like:
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Testing RAM from 0xA00000 to 0xB00000
-Data bus test passed
-Address bus test passed
-Byte and half-word access test passed
-Testing each bit in memory device. . . passed
-Testing memory using DMA.
channels ... tx handle=0x816e28, rx handle=0x816e44
DMA write buffer:0x8081a2a0, read buffer:0x8081b2a8
[tx: 0xa00000](tx:rc=0)(rx:rc=0)
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You can see that the read/write buffers are way outside the testing area, and I can't believe the stack has extended down from 0xFFFFFF to impact on 0xB00000. I'm not currently trying to exhaustively test DMA to/from the SDRAM, just get it working at all...
Still, if there's a shadow of doubt, it may be worth trying :)
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If your VGA controller has a streaming input then maybe something like this would work well for you:
http://www.alterawiki.com/wiki/modular_sgdma_video_frame_buffer --- Quote End ---
Yes, I saw that one :) I was going to try and get it working with "simple" DMA before going to the scatter/gather option... It would be nice to start it going and forget about it from then on, though. I also wasn't sure whether a DDR SDRAM would be required, or whether it's just what the design was demonstrated on. The DE0 only has an SDR SDRAM :(
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Instead of phase shifting the SDRAM clock I would recommend writing .sdc constraints for the SDRAM instead. The fitter will move the logic of the SDRAM controller around to meet the offchip timing. This will require you to read the SDRAM device data sheet to find out it's timing so that you can key them into the custom timing constraints. If you are new to Timequest this might take a while to learn and maybe what I refer to as the "lick your finger and hold it up to the wind" method (phase shifted clock) would be the quickest solution for you.
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New to Timequest, and to just about everything else here... I was actually pretty pleased with myself for getting the PLL clocks worked out in Timequest [grin].
However, I've just tried setting the phase-shift to -2.5ns and then -3.5ns, without any success on either setting, and it reads just fine at either setting when not using DMA. I guess DMA puts the SDRAM under a lot more strain than just single reads/writes...
Are there any "gotchas" that newbies like myself might be tripped up by, that seasoned designers do as a matter of course ? Or is it really just down to the SDRAM being *that* picky about working ?
Cheers
Simon
Honored Contributor
