DE5a-Net-DDR4 PCIe design

Hello,

Thanks for the reply. The behavior is very consistent. Whenever I transfer over 2K bytes it seems to crash. The weird thing is that my hardware is receiving all the data correctly and writing it back into memory correctly. I verified this by printing the DMA memory regions successfully. Even if I transfer more such as 65K bytes, my interrupt generation logic successfully notifies to operating system that all data has been received successfully. Based on this it seems that the application logic is correct. The FPGA loosing its bit stream is whats causing the kernel panic and crash. The only thing I can think of that would cause this is the FPGA is consuming too much power, but this seems unlikely since the designs is not too large.

Thanks