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Altera_Forum
Honored Contributor
Honored ContributorDE0_Nano: bad PLL jitter
I implemented Terasic's "My First FPGA" tutorial, and the 5Mhz PLL output is erratic. The project uses an ALTPLL to divide the onboard 50MHz oscillator down to 5MHz. I routed the clock to a G...
Altera_ForumHonored Contributor
Honored ContributorShouldn't happen. I would monitor PLL locked signal to get additional information.
Self-reset at least won't hurt. I'm not absolutely sure how the PLL works without a global reset.
