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New Contributor

3 years ago

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DDR4 IBIS Models

I am generating Startisx10 IBIS models for DDR4 pins and there are two pins which same function being assigned to different models: | [Pin] signal_name model_name | A15 ddr4...

allspark_top_wrapper_outputmode-strength-48.zip487 KB

AdzimZM_Altera
3 years ago
Hi Arley,

The IBIS model is correct. Only the name is not generate properly due to some bug from the Quartus.
You can use the model that has been generate from the Quartus.

Regards,
Adzim

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Regular Contributor

3 years ago

Hello ArleySalvador,

Thank you for submitting your question in Intel Community.

I believe there is no error for those pins.

The A15 pin should be assigned to DQS signal while the A17 pin for DQ signal.

For more details, you can direct to Pin Out file for Stratix 10 device and check the pins details.

Link to Pin-Out file: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html

Regards,

Adzim

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New Contributor

3 years ago

Hi Adzim,

According to the EMIF ipcore configuration below, I expect to have I/O pin restriction for DQS X8/X9.

Then according to the 1SG040 pinning table, the pins A15 and A17 are supposed be assigned to DQ models.

Is there any wrong assumption from my side?

Regards,

Arley