Forum Discussion
User1580871742356367
Occasional Contributor
Occasional ContributorDDR4 controller DQS pins
I wonder if the polarity of DQS signal can be inverted inside FPGA (not HPS), for example, bank 3F or 3H.
The DQS_P and DQS_N connection are reversed at one DDR4 device side and there 4 DDR4 devic...
sstrell
Super Contributor
Super ContributorI'm presuming you're using a hard controller and PHY. If so, no, you can't do that. You wouldn't want to either due to extra delay.
