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Altera_Forum
Honored Contributor
Honored ContributorData from FPGA to host
Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- That is up to you. --- Quote End --- OK but I really don't know what difference it makes. What have I to do in one case or the other? --- Quote Start --- If all you need is something to generate an Avalon-MM read or write, then you can use the NIOS II processor to generate the transaction. If your SignalTap II trace is at the Avalon-MM slave interface, then either the CPU or JTAG-to-Avalon-MM master can be used. --- Quote End --- I still can't understand what need the SignalTap II trace is. Here's what I tried first: Download the design in the FPGA. This design was waiting an activity on any observed input signal to start the recording in the "onchip memory" (so told qsys). This memory is too small to capture the whole process so I thought of using the sdram. I thought of using this procedure: 1. download the design in the FPGA 2. start a waiting command in the console 3. start the observed process and record the signals in the sdram 4. detecting the end of the process and then write the content of the sdram in a file on the host computer Does this way of doing it seem to be OK?
