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has the JTAG to Avalon master bridge you use to be implemented?
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Its a standard Qsys component.
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The signals from the fifo have to go to the sdram controller or to the cpu?
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That is up to you.
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The commands you use (as jtag_read or jtag_write) can be used by the cpu or only in the console?
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The NIOS II CPU cannot "see" the JTAG port, since it is inside the FPGA. You need to use System Console from the host. If all you need is something to generate an Avalon-MM read or write, then you can use the NIOS II processor to generate the transaction. If your SignalTap II trace is at the Avalon-MM slave interface, then either the CPU or JTAG-to-Avalon-MM master can be used.
Cheers,
Dave
Honored Contributor
