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Let's go on...
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Ok, glad to hear you managed to resolve that issue.
Once you have the Qsys design synthesized, you can look at the System Console command script and see how it uses Tcl commands that are described in the Altera documentation. Read that documentation and try to understand the scripts. From that you should be able to see how data can be moved back-and-forth between the FPGA and the PC. Then you can figure out if it meets your needs, eg., the interface might be fast enough to continuously transfer data at the rate you need, or if its not, perhaps you can write a snapshot of data to SDRAM and then transfer that snapshot.
Cheers,
Dave
Honored Contributor
