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I need to transfer some words (4 bits for now) at about 10MHz from the FPGA to the host so it can be treated by software application.
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Right, that is what you stated above, however that is a data rate of 40Mbps, which far exceeds the capabilities of the DE0-nano JTAG interface, or of any UART interface you connect to I/O pins. A faster parallel interface would likely be needed.
So, take a step back, and explain "what" it is you are trying to do. What is this 40Mbps data stream? Is it continuous, or are snapshots acceptable? Could it be processed or minimally pre-processed on the FPGA to reduce the data rate over the link?
Or, why use a DE0-nano, why not use a board in a PCIe slot, and use the PCIe bus bandwidth?
Cheers,
Dave
Honored Contributor
