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Hi all,
for C4GX dev kit HSMC port A, pin 96 (HSMA_CLK_IN_P1), 98 (HSMA_CLK_IN_N1), 156 (HSMA_CLK_PIN_P2), 158 (HSMA_CLK_IN_N2), I would like to use these 4 pins as output.
In c4gx reference manual, pg40, Table 2-32, it describes these pins as e.g. LVDS or CMOS clock in 1 or CMOS bit 37.
How or what configuration I need in order to use these clocks input pins as normal general purpose output pin?
thank you
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As before, you need to get the schematics for the C4GX reference board, they have all the information you need.
Find out which FPGA pins those HSMC nets are connected to and if you can, assign them as outputs.
[Edit] I see you have the schematics. Create a series of outputs and assign them to the pins those nets are connected to. If Quartus allows the pin assignment in the FPGA build then you're done. [/Edit]
Nial
Honored Contributor
