cyclone 10gx-lvds_cdr

Hi there

We looked at the design and the issue seems to be from the generated SDC file of the LVDS SERDES IP. We created a standalone LVDS SERDES design with the same setting as your design does, and we don't see such error exist.

Few things we want to point out:

1. there are unconstraint clocks in the design, though those unconstraint clocks don't seem related to this issue after we fixed them.

2. we switched the LVDS SERDES IP from soft-CDR to RX DPA mode, and we see that this error goes away.

3. We created a simple design with just the LVDS SERDES IP with all the similar setting, and we don't see this error happened. We compare the generated SDC file with the one in your design, and both SDC files are the same.

Questions:

1. Do you upgrade the IP which is generated from other Quartus version? From the Quartus setting file, we saw that the original Quartus version was 17.1.

thanks

Eng Wei