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Altera_Forum's avatar
Altera_Forum
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18 years ago

CFI Flash on Cyclone III starter board

Hi

I have some problems with the memory on the Cyclone III starter kit. Each time I try to download data to the external memory in NIOS IDE I get the "verify failed between address...." failure.

I thought that my timing was the problem so to make the design simple I have tried to make a project with a Nios processor, some LEDs and an interface to the external flash. I have made it all in SOPC 7.1 and have chosen the preset for the Intel flash on the starter kit. I expect that I do not have to set up timing constraints in quartus II as timing is taken care of in the SOPC builder GUI.

I do not use Address0 for the flash as the data bus in the flash is 16 bit wide.

I set all dual purpose pins to be used as regular I/O and configuration to be active parallel.

Do I do anything wrong? I can program the FPGA, but when I download the software to the flash then I get the mentioned failure, but if I download to the onchip memory then the program runs.

I have also tried to make a custom made flash interface where I chose some larger wait and hold times on the timing page, but it still does not work.

Does anybody have ideas of what the problem should be.

Best regards

Tom

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi Tom,

    I'm assuming that you have only flash as the memory subsystem for Nios II (no other rd/wr memory or DRAMs) and you have set Reset address as flash base address in the Nios II "More CPU" settings. So when you download program to Nios II, IDE tries to verify from flash, which actually does not get programmed by downloading dialogue. If you really want to program the flash, then use flash programmer from Nios II IDE>> Tools menu. So you could try following: First program the flash with your program using the Flash programmer from Nios II IDE Tools menu. Then try running the program again. Since the flash is already programmed with the same program that is being verified, you won't get verify fail error and you will be able to run it.

    Usually you run the program from flash when it's production ready. If you are developing a program, it's always good idea to have a SRAM/DRAM in the system and run the program from the same. This will save time and help you omit flash programming each time you modify/update your program. You could refer to Nios II resources and probably Nios Forum for more details.

    Hope this will help.

    Cheers,

    BD
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    HI BD

    That works. Thanks a lot. :)

    I have also made my SSRAM work. I have some problems with my license so I used the subscription version of Quartus II with a web edition license and kept getting the "verify failed" error with the SSRAM. Now the ssram works after I have uninstalled the subscription version and installed the web edition version.

    Regards

    Tom
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi Tom,

    How did you access the SSRAM on this board?

    Did you create a component in the Component Editor?

    If you did, could you post your _hw.tcl, as I am still gettinguse to the new signal descriptions etc.

    TTFN.

    NN
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi i am newbie to FPGA Design.But i am interseted in the FPGA design .Please any can guide me to clear startup

    Regards

    Mohan