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Altera_Forum's avatar
Altera_Forum
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14 years ago

C4GX kit dev + TSE without external memory

Hi all, I got a new mistake. I start with the board update portal design from altera. I don't understand why in this design there is a big onchip memory and SSRAM. Can someone explain...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

hi,

I have the same problem... my program stall at 

/* Wait for the descriptor (chain) to complete */
while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(dev->base) &
ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) );

I work on a cycloneIII 3c120 demoboard, the sopc is about the same as kmk_drdo's has posted; but I haven't so much on-chip-ram so I use an external ssram (which work with other app).

any hints to solve the problem?

Ale.