Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

C4GX kit dev + TSE without external memory

Hi all, I got a new mistake. I start with the board update portal design from altera. I don't understand why in this design there is a big onchip memory and SSRAM. Can someone explain...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for the picture but I can't see anything it's too small.

I found something interresting, the sgdma's (rx and tx) are connected to the uas port of the ssram and ext_flash.

I've started this test with the original project. I disconnect rx and tx sgdma from ext_flash.

Recompile and test ----> don't work and stuk like usual (wait descriptor chain).

I go back to Qsys and make ctrl+z to have my connection restored.

Recompile and test ----> don't work too, same problem.

Interresting.

I investigate.