Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

C4GX kit dev + TSE without external memory

Hi all, I got a new mistake. I start with the board update portal design from altera. I don't understand why in this design there is a big onchip memory and SSRAM. Can someone explain...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The SSS application requires around 379 Kbytes and my on-chip memory is 512 Kbytes.

In Sopc builder I've got exception vector to on-chip memory + offset (0x120).

In BSP file, I configure in the linker .bss, .rwdata .text .rodata .heap .stack to the on-chip memory.

Maybe my memory is not enough big?