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Altera_Forum
Honored Contributor
Honored ContributorArria V SoC Transceivers
I am trying to bring up a transceiver project on the Arria V SoC development board and have thus far had no luck. I've tried to use a transceiver toolkit example project with new device and pin assig...
Altera_ForumHonored Contributor
Honored ContributorUpdate:
I gave up on the transceiver toolkit, but am now watching the signals in SignalTap. Using a basic reference design for the Custom Phy, I am able to see both tx_ready and rx_ready are a logic 1. However, this is using the GIGE protocol at around 1 Gbps and utilizes a different reference clock than the one I want to use. If I try to change the protocol, data width, or reference clock frequency, rx_ready is never set. Has anyone seen this before or have any insight into something to try?
