Occasional Contributor
Occasional ContributorHi,
I also use the driver from reference design, but mine is called software_hbm2_ddr4 as the attached file.
Are you using the first one of following reference designs?
https://fpgacloud.intel.com/devstore/platform/?acds_version=any&family=stratix-10&board=104
Mine is AN881: PCIe AVMM DMA Gen3x16 DDR4 and HBM2 .
Our message is:
Occasional ContributorHi,
After we enabled BIOS "above 4G decoding" setting, the BAR address and memory space could be allocated.
Besides, we modified PCIe class code from default 0xff0000 to 0x068000 (Bridge device).
Otherwise BIOS of our motherboard doesn't allocate BAR of FPGA.
It seems you don't have this class code issue.
But capabilities are still "access denied".
Would it be a problem? Or it's normal?
And then, we can change BAR number after above modification,
but link test and DMA functions still fail.
All the read value of link test is 0xffffffff, which is error code replied by system.
Is your situation the same?
Besides, the test program shows " Stopping DMA run due to error." when we trigger DMA function.
