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Altera_Forum
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17 years ago

Altera PCI Express Development Kit: Linux DMA Driver

Hi, I am a newbie to FPGA design and implementation. While installing the PCI express board on LINUX machine, I don't see Demo application driver for DMA read and write for LINUX (Manual talk...
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Altera_Forum
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16 years ago

I have seen a problem with the high performance PCIe reference design chaining DMA on an Aria IIGX development board. If you program the upper address for a descriptor table entry (which would be required under a 64 bit OS or 32 bit+PAE kernel), the DMA engine should generate a 4DW read request (for PC -> endpoint transfer), but it does not, it instead only generates a 3DW read request, so in essence it is reading the wrong memory location. I have captured the transactions on a PCIe protocol analyzer.

I am using 32 bit Linux with PAE enabled. You just won't see it under most Windows since only 64 bit Windows or server Windows with PAE enabled would have pages above 4G.

I haven't tried the other direction (endpoint -> PC) yet. I need to protect the system since if the same bug happens, the OS will likely crash and burn once the wrong memory gets trashed.