Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi all,
I'm using the PCIe high performance reference design (on the Arria II GX board) on a host that uses legacy mode interrupts. I see the Arria II GX generate an "assert INTA" message followed immediately by a "deassert INTA" message once the descriptor table entry gets processed (I have interrupts only enabled on the last entry in the table). The host sees the interrupt and the ISR is called. However, I don't know what to do to acknowledge the legacy mode interrupt to the reference design, and the FPGA keeps doing the assert/deassert cycle every 39.5uS until the DMA controller is reset. I didn't see any documentation on acknowledging interrupts. Anyone know what the chaining DMA design wants (in legacy interrupt mode)? Thanks, Tony