Forum Discussion

veriguy's avatar
veriguy
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Agilex F-Series FPGA Dev Kit example design compilation

It looks like the example design supplied with dev-kit "golden_top" has not actually been compiled. There is a typo in the verilog file that causes a syntax error during rtl analysis & synthesis phas...
  • veriguy's avatar
    veriguy
    4 years ago

    Able to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.

veriguy's avatar
veriguy
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Able to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi there

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Thanks.

Eng Wei