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veriguy
Occasional Contributor
Occasional ContributorAgilex F-Series FPGA Dev Kit example design compilation
It looks like the example design supplied with dev-kit "golden_top" has not actually been compiled. There is a typo in the verilog file that causes a syntax error during rtl analysis & synthesis phas...
Able to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.
veriguyOccasional Contributor
Occasional ContributorAble to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.
EngWei_O_Intel
Frequent Contributor
Frequent ContributorHi there
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Thanks.
Eng Wei
