veriguy
Occasional Contributor
Occasional ContributorAgilex F-Series FPGA Dev Kit example design compilation
It looks like the example design supplied with dev-kit "golden_top" has not actually been compiled. There is a typo in the verilog file that causes a syntax error during rtl analysis & synthesis phas...
Able to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.
