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veriguy
Occasional Contributor
Occasional ContributorAgilex F-Series FPGA Dev Kit example design compilation
It looks like the example design supplied with dev-kit "golden_top" has not actually been compiled. There is a typo in the verilog file that causes a syntax error during rtl analysis & synthesis phas...
Able to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.
veriguyOccasional Contributor
Occasional ContributorHi Eng Wei,
For some reason the archived project does show the above error. Taking a step back, I am trying to compile a project for Agilex F-series development kit. There are some example designs included, however am not able to successfully compile any of the few I tried,as they all ran into some kind of error or the other. Can you please direct me to an example design or project template that would have the pin assignments and other recommended settings and that I can use as starting point for my design?
