ADC interfacing and DDR_LVDS

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DDIO do not have a internal PLL

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SERDES with factor 1:2 neither has if implemented in logic cells. With Arria/Stratix, you'll can use dedicated SERDES hardware and then need a PLL. This may be reasonable a highest speed, utilizing the SERDES dynamic phase alignment feature.

With SERDES in logic cells, which isn't but DDIO, differential CLKOUT can directly used as DDR sampling clock.