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ZC0001's avatar
ZC0001
Icon for New Contributor rankNew Contributor
6 years ago

About the clk scheme of the cyclone 10 GX development kit

Hi, all On Cyclone® 10 GX Development Kit Board,there are two clk net schemes for FPGA，one is using Si5340 and another is using Si53307-B-GM and Si5332A-C-GM2R . I want to know why there are two sch...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

You can refer to dev kit user guide doc page 26 - figure 5 clock distribution to understand the clock generator chip connection

Different clock generator chip is used to provide clock source to different FPGA pin location.

  • You can find detail connection in dev kit schematic as well

So in the end it's really depend on which FPGA pin that you plan to use and then you can check which clock generator chip is used to clock your FPGA pin accordingly

Thanks.

Regards,

dlim