Forum Discussion

New Contributor

5 years ago

10G transceiver in S10MX

Hi, I am bringing up the transceiver in the Stratix 10 MX development kit using both approaches below APPROACH (A) I followed the 25G Ethernet Intel Stratix 10 FPGA IP User Guide. My impleme...

SengKok_L_Intel

Regular Contributor

5 years ago

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Forum Discussion

10G transceiver in S10MX

Recent Discussions

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work

PCIe Root Complex on DK-A5E013BM16AEA