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XNguy4's avatar
XNguy4
Icon for New Contributor rankNew Contributor
5 years ago

10G transceiver in S10MX

Hi, I am bringing up the transceiver in the Stratix 10 MX development kit using both approaches below APPROACH (A) I followed the 25G Ethernet Intel Stratix 10 FPGA IP User Guide. My impleme...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago
  1. To narrow down the problem, this is still good to know if the design can operate as expected by using the QSFP loopback module?
  2. Does the rx_is_lockedtodata is always asserted? Or it is toggling? What is the status of the tx_fifo_full and rx_fifo_full?
  3. Do you observe the avalon_st_tx_ready signal is asserted?
  4. Could you do a sanity check by changing the VCCR_GXB to 1_1v?

Regards -SK