Most RecentWhy is the clock not running in my design when I use the Clock Control Intel® FPGA IP?Is the hard transceiver 8B/10B encoder/decoder in Stratix, Arria, and Cyclone family transceiver devices Fibre Channel compliant?Arria 10 and Cyclone 10 GX EMIF Simulations May Fail with Certain Versions of Riviera-PROWhy can't I export the wave image in bmp format in the ModelSim*-Intel® FPGA Edition and Questa*-Intel® FPGA Edition simulator?Is the Legacy Mode of HPS SPI controller still supported in SOC devices?Half-Duplex Mode Post Collision IssuesWhy do my transactions through the Arria 10 light weight axi interface function incorrectly in hardware?Do the data and the source clock both need to be present at the inputs for the dynamic phase alignment (DPA) circuitry to operate correctly in Stratix GX devices?Do Intel® MAX® 10 devices have an exposed pad at the bottom of the 144-pin EQFP (E144) package?Arria V GZ and Stratix V Hard IP for PCIe IP Core Do Not Cycle through Gen1-Gen3 Data Rates in CBB Testing
