Most RecentWhy does the SignalTap II Logic Analyzer not allow RAM type to be selected for Stratix V devices?Why is my PLL losing lock during or after performing PLL reconfiguration in my Stratix or Stratix GX device?L2 Cache Controller Revision Incorrectly Listed as r3p2Why does the MAC TX of the F-Tile Ethernet FPGA Hard IP halt its transmission of control frames (0x8808) upon receiving PAUSE frames from the link partner?How do I change the color of the Field View in the Quartus® II software Timing Closure Floorplan?Why does my Altera Hard IP for PCI Express not enter compliance loopback in Gen 3 mode?Why doesn’t the F-Tile Transceiver Toolkit eye viewer feature work in the Intel® Quartus® Prime Pro Edition Software v21.4 ?Fatal Error: Read data comes back but dynamic OCT ctrl is not in read modeWhy does my USB debug Master not work in the System console on the Cyclone® V GX FPGA development kit?Why does the E-Tile Ethernet IP for Intel Agilex® 7 FPGA IP core fail when performing dynamic reconfiguration between 100G-PAM4 and 4x25G NRZ modes?
