Most RecentError! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILYWhy is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock?Why do I see rx_ready not asserting, or incorrect TX data rates in Agilex® 7 F‑Tile or Agilex® 5/3 FPGA GTS device transceiver simulations using the Quartus® Prime Pro 25.3.1 or earlier software with Siemens QuestaSim® Altera Edition software?Why can’t the Agilex® 5 FPGA E‑Series 065B Modular Development Kit be configured using the configuration file generated from the GTS AXI Streaming IP for PCI Express* design example?Why does the BAM (Bursting Avalon‑MM Master) module of the GTS AXI Multichannel DMA IP for PCI Express* fail to generate Completion TLPs in a PCIe Root Port implementation?Why does niosv-download return “Invalid reset option” when executing reset from debug module?Why do the Configuration Intercept Interface, Control Shadow Interface, Configuration Extension Bus Interface, and VirtIO features not operate as expected when Configuration via Protocol is enabled in the GTS AXI Streaming IP for PCI Express*?Which Protocols Support Spread Spectrum Clocking (SSC) on Agilex® 5 and Agilex® 3 FPGA Devices?Why does boundary scan fail or report length mismatches when including F-Tile FHT transceivers in the scan chain of Agilex® 7 FPGA devices when using Quartus® Prime Pro software version 26.1 or earlier?Why does the HPS boot up delay after trigger HPS cold reset via the external reset pin?
