Most RecentWhy does the O-RAN Intel® FPGA IP give incorrect values when Block floating-point compression is turned on?How can I connect two Transceiver Toolkit System Consoles to two Altera devices with two USB ports on the same computer, when each device is programmed with the same FPGA image?Why does the JESD204B Intel® FPGA IP Example Design fail to operate correctly when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices?Why am I unable to set the 'Size of address pages' to a value between 17 and 21 bits for the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode?Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic.Are there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script?Why does the Intel® Arria® 10 and the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design report ignored SDC constraint warnings?Why is the “o_rx_pause” width as double as the expected value for 40GE designs when using the F-Tile Ethernet FPGA Hard IP and F-Tile Ethernet Multirate FPGA IP?During simulation of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, l8_rx_fcs_error goes to 'X' when l8_rx_fcs_valid is '1'Why do the FIR II Megacore’s parameters revert to default values after upgrading to a newer version of the Quartus software?
