Most RecentDuring simulation of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, l8_rx_fcs_error goes to 'X' when l8_rx_fcs_valid is '1'Why do the FIR II Megacore’s parameters revert to default values after upgrading to a newer version of the Quartus software?Why after collision occurs for Triple Speed Ethernet IP MegaCore in half-duplex mode, MAC function continuously sends data out through the MII interface even when no data are sent to the MAC function?Can I run boundary scan on a JTAG chain that contains a Stratix II, Stratix, Cyclone II or Cyclone devices and is longer then 8 devices?Why does the Intel® PCIe* Hard IP run into recursive replay timer timeout, replay num rollover and link recovery when sending traffic?Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/altera_arch_common/altera_arch_re_network_routing_constraints.cpp, Line: 1421Why are interrupts not working in my PCI Express End PointWhich pins are powered by the VCCRSTCLK_HPS supply?Why are the instantiated IP blocks in a Platform Designer System design showing up as Generic Components?Link Training Issues May Occur with Stratix V Hard IP for PCIe Gen2 Endpoints in Gen3 Systems
