Most RecentHow to set HPS SDRAM PLL reference clock resource for Cyclone® V SoC device?Does Altera provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI?Can I use open drain on Arria 10 devices' I/O to pull-up signal to voltage level higher than VCCIO?Why does the Intel® Arria® 10 DisplayPort IP with Bitec* daughter card have no video output for both 1-lane or 2 lanes configurations?The ALTGX MegaWizard Plug-In Manager shows invalid selections on the Rx and Tx Analog pages for Cyclone IV GXWarning: Support for IP core "NCO" (6AF7_0014) in device family Arria II GX is preliminary and specifications are subject to changeArria 10 device secondary files are not created during design compilationDo Altera devices support programmable internal weak pull down resistors on I/O pins?Error: native_10g_322_ls_inst: The current value "" (10312.5) for parameter "Data rate" (set_data_rate) is invalid. Possible valid values are: "" (1000.0:8000.0).When using UniPHY IP in Stratix V devices, what are the options for changing the calibrated OCT termination values from the default values ?
