Most RecentWhy a 2-3x Bandwidth Increase in CXL + Compression is Compelling for AI, HPC, and Data CentersUnlock More FPGA & AI Performance with the Expanded Agilex™ 5 D-Series FamilyAltera Releases Quartus® Prime Pro Edition and FPGA AI Suite version 25.3: Faster Compiles, SmarterReplace RFSoC FPGAs with Altera’s Agilex™ 9 Direct RF Medium-band SoC FPGAsTÜV-Certified Dual-Axis Motor Control with Functional Safety on Agilex™ 5 SoC FPGAsMAX® 10 FPGA New Packages: Up to 59% Higher I/O Density vs. CompetitorsLower mMIMO OpEx with AI-based Advanced Channel Estimation on a SoC FPGACAST & Fraunhofer IPMS Showcase Flexible, Resource-Efficient TSN on Altera’s Cost Optimized FPGAsChannel Estimation with AI on Altera SoC FPGAAddressing PQC and CRA with Crypto-Agile Security in Agilex™ Devices
